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18-bit, 2 msps sar adc preliminary technical data ad7641 rev. pr e information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 18-bit resolution with no missing codes 2.5v internal low drift refernce throughput: 2 msps (warp mode) 1.5 msps (normal mode) inl: 2 lsb typical s/(n+d): 93 db typical @ 100 khz ( v ref = 2.5 v ) thd: ?100 db typical @ 100 khz differential input range: v ref (v ref up to 2.5 v) no pipeline delay ( sar architecture ) parallel (18-, 16-, or 8-bit bus) serial 5 v/3.3 v/2.5 v interface spi?/qspi?/microwire?/dsp compatible on-board low drift reference with buffer and temperature sensor single 2.5 v supply operation power dissipation: 100 mw typical @ 2 msps power-down mode 48-lqfp and lfcsp packages speed upgrade of the ad7674 pin-to-pin compatible with the ad7621 applications medical instruments high dynamic data acquisition instrumentation spectrum analysis ate functional block diagram switched cap dac 18 control logic and calibration circuitry clock ad7641 d[17:0] busy rd cs mode0 ognd ovdd dgnd dvdd avdd agnd ref refgnd in+ in- pd reset serial port parallel interface cnvst pdbuf refbufin warp impulse mode1 pdref ref temp figure 1. table 1. pulsar selection ksps type 100 to 250 500 to 570 800 to 1000 >1000 pseudo differential ad7651 ad7660/61 ad7650/52 ad7664/6 6 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 ad7621 18 bit ad7678 ad7679 ad7674 ad7641 multichannel/ simultaneous ad7654 ad7655 general description the ad7641 is a 18-bit, 2 msps, charge redistribution sar, fully differential analog-to-digital converter that operates from a single 2.5 v power supply. the part contains a high-speed 18- bit sampling adc, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. it features a very high sampling rate mode (warp) and a fast mode (normal) for asynchronous conversion rate applications. the ad7641 is hardware factory calibrated and comprehensively tested to ensure ac parameters such as signal-to-noise ratio (snr) and total harmonic distortion (thd) in addition to the more traditional dc parameters of gain, offset and linearity. operation is specified from ?40c to +85c. product highlights 1. high resolution and fast throughput. the ad7641 is a 2 msps, charge redistribution, 18-bit sar adc (no latency). 2. superior inl. the ad7641 has a maximum integral nonlinearity of 2 lsb with no missing 18-bit codes. 3. single-supply operation. operates from a single 2.5 v supply. also features a power-down mode. 4. serial or parallel interface. versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial interface arrangement compatible with either 2.5 v, 3.3 v, or 5 v logic.
ad7641 preliminary technical data rev. pr e | page 2 of 24 table of contents specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology .................................................................................... 10 circuit information ........................................................................ 11 converter operation...................................................................... 12 modes of operation ................................................................... 12 transfer functions...................................................................... 12 typical connection diagram........................................................ 14 analog inputs.............................................................................. 14 driver amplifier choice............................................................ 14 single to differential driver...................................................... 15 voltage reference ....................................................................... 15 temperature sensor ................................................................... 15 power supply............................................................................... 16 conversion control ................................................................... 16 interfaces.......................................................................................... 17 digital interface .......................................................................... 17 parallel interface......................................................................... 17 serial interface ............................................................................ 18 master serial interface............................................................... 18 slave serial interface .................................................................. 18 microprocessor interfacing....................................................... 21 application hints ........................................................................... 22 layout .......................................................................................... 22 evaluating the ad7641 performance ...................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24
preliminary technical data ad7641 rev. pr e | page 3 of 24 specifications table 2. ? 40c to +85c, v ref = avdd, avdd = dvdd = ovdd = 2.5 v, unless otherwise noted. parameter conditions min typ max unit resolution 18 bits analog input voltage range v in+ C v in Cv ref +v ref v operating input voltage v in+, v in to agnd -0.1 avdd v analog input cmrr f in = 100 khz 60 db input current 2 msps throughput tbd a input impedance 1 see analog inputs section throughput speed complete cycle in warp mode 500 ns throughput rate in warp mode 0.001 2 msps time between conversions in warp mode 1 ms complete cycle in normal mode 667 ns throughput rate in normal mode 0 1.5 msps dc accuracy integral linearity error C3 2 +3 lsb 2 differential linearity error C1 lsb no missing codes 18 bits transition noise v ref = avdd 56 v gain error, t min to t max 3 tbd % of fsr gain error temperature drift 0.5 ppm/c zero error, t min to t max 3 tbd tbd lsb zero error temperature drift 1.6 ppm/c power supply sensitivity avdd = 2.5v 5% 5 lsb ac accuracy signal-to-noise f in = 100 khz, v ref =avdd 93 db 4 v ref =2.048v 91.3 db spurious free dynamic range f in = 100 khz 100 db total harmonic distortion f in = 100 khz C100 db signal-to-(noise+distortion) f in = 100 khz, 93 db f in = 100 khz, -60 db input 33 db -3 db input bandwidth 50 mhz sampling dynamics aperture delay 1 ns aperture jitter 5 ps rms transient response full-scale step 160 ns overvoltage recovery 160 ns reference external reference voltage range ref tbd 2.048 avdd v ref current drain 2 msps throughput tbd a ref voltage with reference buffer refbufin=1.2v 2 2.048 2.1 v reference buffer input voltage refbufin tbd 1.2 tbd v refbufin input current C1 + 1 a internal reference internal reference voltage @ 25c 1.197 1.2 1.203 v internal reference temp drift C 40c to +85c 3 ppm/c refbufin line regulation avdd = 2.5v 5% 15 ppm/v refbufin output resistance k? turn-on settling time 5 ms long-term stability 1,000 hours 100 ppm/1000hours
ad7641 preliminary technical data rev. pr e | page 4 of 24 parameter conditions min typ max unit hysterisis 50 ppm temperature pin voltage output @ 25c 300 mv temperature sensitivity 1 mv/c temp pin output resistance 4 k? digital inputs logic levels v il C0.3 +0.6 v v ih +1.7 5.25 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 500 a 0.4 v v oh i source = -500 a ovdd C 0.3 v power supplies specified performance avdd 2.37 2.5 2.63 v dvdd 2.37 2.5 2.63 v ovdd 2.3 3.6 v operating current 7 2 msps throughput avdd 15 ma dvdd 8 4.5 ma ovdd 130 a power dissipation 7 pdbuf = high @ 2 msps 100 mw pdbuf = low @ 2 msps 108 mw in power-down mode pd = high tbd w temperature range 9 specified performance t min to t max -40 +85 c 1 see analog input section 2 lsb means least significant bit. with the 2.5 v input range, one lsb is 19.07 v. 3 see definition of specifications section. these specifications do not include the error contribution from the external referen ce. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless otherwise specified. 5 parallel or serial 18 bit.. 6 conversion results are available imme diately after completed conversion. 7 in warp mode. 8 tested in parallel reading mode. 9 contact factory for extended temperature range.
preliminary technical data ad7641 rev. pr e | page 5 of 24 timing specifications table 3. C40c to +85c, avdd = dvdd = 2.5 v, ovdd = 2.3 v to 3.6 v, unless otherwise noted. parameter symbol min typ max unit refer to figure 13 and figure 14 convert pulse width t 1 5 ns time between conversion s (warp mode/normal mode) 1 t 2 500/667 note 1 ns cnvst low to busy high delay t 3 30 ns busy high all modes except in master serial read after convert (warp mode/normal mode) t 4 340/465 ns aperture delay t 5 1 ns end of conversion to busy low delay t 6 10 ns conversion time (warp mode/normal mode) t 7 340/465 ns acquisition time (warp mode/normal mode) t 8 70/100 ns reset pulsewidth t 9 10 ns refer to figure 15, figure 16, and figure 17 (parallel interface modes) cnvst low to data valid delay (warp mode/normal mode) t 10 340/465 ns data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 2 15 ns refer to figure 19 and figure 20 (master serial interface modes) 2 cs low to sync valid delay t 14 tbd ns cs low to internal sclk valid delay t 15 tbd ns cs low to sdout delay t 16 tbd ns cnvst low to sync delay (warp mode/normal mode) t 17 tbd sync asserted to sclk first edge delay 3 t 18 tbd ns internal sclk period 3 t 19 tbd tbd ns internal sclk high 3 t 20 tbd ns internal sclk low 3 t 21 tbd ns sdout valid setup time t 22 tbd ns sdout valid hold time t 23 tbd ns sclk last edge to sync delay 3 t 24 tbd ns cs high to sync hi-z t 25 tbd ns cs high to internal sclk hi-z t 26 tbd ns cs high to sdout hi-z t 27 tbd ns busy high in master serial read after convert 3 t 28 tbd ns cnvst low to sync asserted delay (warp mode/normal mode) t 29 tbd ns sync deasserted to busy low delay t 30 tbd ns refer to figure 21 and figure 22 (slave serial interface modes) external sclk setup time t 31 5 ns external sclk active edge to sdout delay t 32 2 7 ns sdin setup time t 33 tbd ns sdin hold time t 34 tbd ns external sclk period t 35 12.5 ns external sclk high t 36 5 ns external sclk low t 37 5 ns 1 in warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time. 2 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode.
ad7641 preliminary technical data rev. pr e | page 6 of 24 absolute maximum ratings table 4. ad7641 stress ratings 1 parameter rating analog inputs in+ 2 , in- 2 , ref, refbufin, refgnd to agnd avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd C0.3 v to +2.7 v ovdd C0.3 v to +3.8 v digital inputs C0.3 v to 5.5v internal power dissipation 3 700 mw internal power dissipation 4 2.5 w junction temperature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect device reliability 2 see analog inputs section. 3 specification is for device in free air: 48-lead lqfp: ja = 91c/w, jc = 30c/w. 4 specification is for device in free air: 48-lead lfcsp: ja = 26c/w. i oh 500 a i ol to output pin 1.4v c l 50pf * * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 50pf maximum. 500 a figure 2. load circuit for digital interface timing sdout, sync, sclk outputs, c l =10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay figure 3. voltage reference levels for timing esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad7641 rev. pr e | page 7 of 24 pin configurations and function descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvs t pd reset cs rd dgnd agnd avdd mode0 mode1 d0/ob/2c nc = no connect d1/a0 d2/a1 d3 d4/divsclk[0] busy d17 d16 d15 ad7641 d5/divsclk[1] d14 d6/ext/int d7/invsync d8/invsclk d9/rdc/sdin ognd ovdd dvdd dgnd d10/sdout d11/sclk d12/sync d13/rderror pdbuf pdref refbufin temp avdd in+ agnd agnd nc in- refgnd ref nc warp figure 4. pin configuration table 5. pin function descriptions pin no. mnemonic type 1 description 1, 36, 41, 42 agnd p analog power ground pin. 2, 44 avdd p input analog power pins. nominally 2.5 v 7, 40 nc no connect 3 mode0 di data output in terface mode selection. 4 mode1 di data output in terface mode selection: interface mode # mode0 mode1 description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 byte interface 3 1 1 serial interface 5 d0/ob/ 2c di/o when mode=0 (18-bit interface mode), this pin is bit 0 of the parallel port data output bus and the data coding is straight binary. in all other modes, this pin allows choice of straight binary/binary twos complement. when ob/ 2c is high, the digital output is stra ight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 6 warp di conversion mode selection. when high, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion ra te must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. 8 d1/a0 di/o when mode=0 (18-bit interface mode), this pin is bi t 1 of the parallel port data output bus. in all other modes, this input pin controls the form in which data is output as shown in table 6. 9 d2/a1 di/o when mode=0 or mode=1 (18-bit or 16-bit interface mode), this pin is bit 2 of the parallel port data output bus. in all other modes, this input pin cont rols the form in which data is output as shown in table 6. 10 d3 do in all modes except mode=3, this outp ut is used as bit 3 of the parallel port data output bus. this pin is always an output regard less of the interface mode. 11, 12 d[4:5] or divsclk[0: 1] di/o in all modes except mode=3, these pins are bi t 4 and bit 5 of the parallel port data output bus. in mode=3 (serial mode), when ext/ int is low, and rdc/sdin is low, which serial master read after convert, these inputs, part of the serial port, are us ed to slow down if desired the internal serial clock clocks the data output. in other seri al modes, these pins are not used.
ad7641 preliminary technical data rev. pr e | page 8 of 24 pin no. mnemonic type 1 description 13 d6 or ext/ int di/o in all modes except mode=3, th is output is used as bit 6 of th e parallel port data ouput bus. when mode=3 (serial mode), this in put, part of the serial port, is used as a digital select input for choosing the internal or an ex ternal data clock. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d7or invsync di/o in all modes except mode=3, th is output is used as bit 7 of th e parallel port data output bus. when mode=3 (serial mode), this inp ut, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 d8 or invsclk di/o in all modes except mode=3, th is output is used as bit 8 of th e parallel port data output bus. when mode=3 (serial mode), this inp ut, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. 16 d9 or rdc/sdin di/o in all modes except mode=3, th is output is used as bit 9 of th e parallel port data output bus. when mode=3 (serial mode), this inp ut, part of the serial port, is used as either an ex ternal data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 18 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the re ad mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data can be output sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital powe r. nominally at the same supply than the supply of the host interface (2.5 v or 3 v). 19 dvdd p digital power. nominally at 2.5 v. 20 dgnd p digital power ground. 21 d10 or sdout do in all modes except mode=3, th is output is used as bit 10 of th e parallel port data output bus. when mode=3 (serial mode), this output, part of the serial port, is used as a se rial data output synchronized to sclk. conversion results are stored in an on-chip shift register. the ad7641 provides the conversion result, msb first, from its internal sh ift register. the data format is determined by the logical level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated sclk risi ng edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk fa lling edge and valid on the next rising edge. 22 d11 or sclk di/o in all modes except mode=3, th is putput is used as the bit 11 of the parallel port data output bus. when mode=3 (serial mode), this pin, part of the se rial port, is used as a se rial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logi c state of the invsclk pin. 23 d12 or sync do in all modes except mode=3, this output is used as the bit 12 of the parallel port data output bus. when mode=3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains hi gh while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 d13 or rderror do in all modes except mode=3, this output is used as the bit 12 of th e parallel port data output bus. in mode=3 (serial mode) and when ext/ int is high, this output, part of the serial port, is used as a incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25-28 d[14:17] do bit 14 to bit 17 of the parallel port data output bus. these pins ar e always outputs regardless of the interface mode. 29 busy do busy output. transitions high when a conversion is started, and rema ins high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock.
preliminary technical data ad7641 rev. pr e | page 9 of 24 pin no. mnemonic type 1 description 33 reset di reset input. when set to a logic high, reset the ad 7641. current conversion if any is absorbed. if not used, this pin could be tied to the dgnd. 34 pd di power-down input. when set to a logic high, pow er consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. a falling edge on cnvst puts th e internal sample/hold into the hold state and initiates a conversion. 37 ref ai reference input voltage and internal reference buffer output. apply an external reference on this pin if the internal reference buffer is not used. shou ld be decoupled effecti vely with or without the internal buffer. 38 refgnd ai reference input analog ground. 39 in- ai differential negative analog input. 43 in+ ai differential negative analog input. 45 temp ao temperature sensor analog output. 46 refbufin ai internal reference output and reference buffer input voltage. the internal reference buffer has a fixed gain. it outputs 2.048v typically wh en 1.2v is applied on this pin. 47 pdref di this pin allows the choice of internal or external voltage references. when low, the on-chip reference is turned on. when high, the internal reference is switched off and an exte rnal reference must be used. 48 pdbuf di this pin allows the choice of buffering an internal or external reference with the internal buffer. when low, the buffer is selected. when high, the buffer is switched off. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = dig ital output; p = power. table 6. data bus interface definition mode mode0 mode1 d0/ob/ 2c d1/a0 d2/a1 d[3] d[4:9] d[10:11] d[12:15] d[16:17] description 0 0 0 r[0] r[1] r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 18-bit parallel 1 0 1 ob/ 2c a0:0 r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 16-bit high word 1 0 1 ob/ 2c a0:1 r[0] r[1] all zeros 16-bit low word 2 1 0 ob/ 2c a0:0 a1:0 all hi-z r[10:11] r[12:15] r[16:17] 8-bit high byte 2 1 0 ob/ 2c a0:0 a1:1 all hi-z r[2:3] r[4:7] r[8:9] 8-bit mid byte 2 1 0 ob/ 2c a0:1 a1:0 all hi-z r[0:1] all zeros 8-bit low byte 2 1 0 ob/ 2c a0:1 a1:1 all hi-z all zeros r[0:1] 8-bit low byte 3 1 1 ob/ 2c all hi-z serial interface serial interface r[0:17] is the 8-bit adc value stored in its output register.
ad7641 preliminary technical data rev. pr e | page 10 of 24 terminology integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. gain error the first transition (from 000 . . . 00 to 000 . . . 01) should occur for an analog voltage 1/2 lsb above the nominal C full scale (?2.047992 v for the 2.048v range). the last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 ? lsb below the nominal full scale (2.047977 v for the 2.048v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. zero error the zero error is the difference between the ideal mid-scale input voltage (0 v) and the actual voltage producing the mid- scale output code. spurious free dynamic range (sfdr)/ the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: [] ( ) ) 02 . 6 / 76 . 1 / ? + = db d n s enob and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the ad7641 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient the change of the internal reference output voltage v over the operating temperature range and normalized by the output voltage at 25c, expressed in ppm/c. the equation follows: () ( ) ( ) () () 6 1 2 1 2 10 25 / ? ? = t t c v t v t v c ppm tcv where: v(25c) = v at 25c v(t 2 ) = v at temperature 2 v(t 1 ) = v at temperature 1 reference voltage long-term stability typical shift of output voltage at 25c on a sample of parts subjected to operation life test of 1000 hours at 125c: () ( ) ( ) () 6 0 0 1 10 ? = ? t v t v t v ppm v where: v(t 0 ) = v at 25c at time 0 v(t 1 ) = v at 25c after 1,000 hours operation at 125c reference voltage thermal hysteresis thermal hysteresis is defined as the change of output voltage after the device is cycled through temperature from +25c to - 40c to +125c and back to +25c. this is a typical value from a sample of parts put through such a cycle () ( ) () 6 10 25 25 ? = c v c v v ppm v tc hys where: v(25c) = v at 25c v tc = v at 25c after temperature cycle at +25c to -40c to +125c and back to +25c
preliminary technical data ad7641 rev. pr e | page 11 of 24 circuit information the ad7641 is a very fast, low-power, single-supply, precise 18- bit analog-to-digital converter (adc) using successive approximation architecture. the ad7641 features different modes to optimize performances according to the applications. in warp mode, the ad7641 is capable of converting 2,000,000 samples per second (2 msps). the ad7641 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7641 can be operated from a single 2.5 v supply and be interfaced to either 5 v or 3.3 v or 2.5 v digital logic. it is housed in a 48-lead lqfp or a tiny lfcsp packages that combines space savings and allows flexible configurations as either serial or parallel interface. the ad7641 is a pin-to-pin- compatible upgrade of the ad7674. sw + msb 131,072c 65,536c 4c 2c c c in+ lsb comp sw - contro l logi c switches contro l busy output code cnvst ref refgnd msb 131,072c 65,536c 4c 2c c c in - lsb figure 5. adc simplified schematic
ad7641 preliminary technical data rev. pr e | page 12 of 24 converter operation the ad7641 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 5 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary weighted capacitors which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to agnd via sw+ and sw-. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on in+ and in- inputs. when the acquisition phase is complete and the cnvst input goes low, a conversion phase is initiated. when the conversion phase begins, sw+ and sw- are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the inputs in+ and in- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 . . . v ref /262144). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the ad7641 features two modes of operations; warp and normal. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 2 msps. however, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. this mode makes the ad7641 ideal for applications where fast sample rate are required. the normal mode is the fastest mode (1.5 msps) without any limitation about the time between conversions. this mode makes the ad7641 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. transfer functions except in 18 bit interface mode, using the ob/ 2c digital input, the ad7641 offers two output codings: straight binary and twos complement. the ideal transfer characteristic for the ad7641 is shown in figure 6 and table 7. 000...000 000...001 000...010 111...101 111...110 111...111 analog input +fs-1.5 lsb +fs-1 lsb -fs+1 lsb -fs -fs+0.5 lsb figure 6. adc ideal transfer function table 7. output codes and ideal input voltages digital output code (hex) description analog input v ref = 2.048v straight binary twos complement fsr C1 lsb 2.047984 v 3ffff 1 1ffff 1 fsr C 2 lsb 2.047969 v 3fffe 1ffe midscale + 1 lsb 15.625v 20001 00001 midscale 0 v 20000 00000 midscale C 1 lsb -15.625v 1ffff 3ffff -fsr + 1 lsb -2.047984 v 00001 20001 -fsr -2.048 v 00000 2 20000 2 1 this is also the code fo r overrange analog input (v in+ C v in- above v ref C v refgnd ). 2 this is also the code fo r underrange analog input (v in+ C vi n- below -v ref + v refgnd ).
preliminary technical data ad7641 rev. pr e | page 13 of 24 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd cnvst busy sdout sclk rd cs reset pd refbufin 10 d clock ad7641 c/ p/dsp serial port digital supply (2.5v or 3.3v) analog supply (2.5v) dvdd ob/2c note 6 dvdd in+ in- analog input- c c 1nf u2 15 note 5 note 3 50 note 4 ad8021 notes : note 1 : see voltage reference input section. note 2 : c ref is 10 f ceramic capacitor or low esr tantalum. ceramic size 1206 panasonic ecj-3xb0j106 is recommended. see voltage reference input s ection. note 3 : the ad8021 is recommended. see driver amplifier choice section. note 4 : see analog inputs section. note 5 : option. see power supply section. note 6 : optional low jitter cnvst. see conversion control section. analog input+ c c 1nf u1 15 note 3 note 4 ad8021 mode1 mode0 refgnd c ref ref 10 f note 2 pdbuf note 1 pdref c ref 100nf note 1 figure 7. typical connection diagram (inter nal reference buffer, serial interface)
ad7641 preliminary technical data rev. pr e | page 14 of 24 typical connection diagram figure 7 shows a typical connection diagram for the ad7641. different circuitry shown on this diagram are optional and are discussed below. analog inputs figure 8 shows a simplified analog input section of the ad7641. in+ in- r + = 87 c s agnd avdd r - = 87 c s figure 8. ad7641 simplified analog input figure 9. analog input cmrr vs. frequency during the acquisition phase, for ac signals, the ad7641 behaves like a one pole rc filter consisted of the equivalent resistance r+ , r- and c s . the resistors r + and r - are typically tbd ? and are lumped component made up of some serial resistor and the on resistance of the switches. the capacitor c s is typically tbd pf and is mainly the adc sampling capacitor. this one pole filter with a typical -3db cutoff frequency of 50 mhz reduces undesirable aliasing effect and limits the noise coming from the inputs. because the input impedance of the ad7641 is very high, the ad7641 can be driven directly by a low impedance source without gain error. this allows, as shown in figure 7, an external one-pole rc filter between the output of the amplifier and the adc analog inputs to even further improve the noise filtering done by the ad7641 analog input circuit. however, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the ad7641 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the ad7641 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 18-bit level (0.0004%). in the amplifiers datasheet, the settling at 0.1% or 0.01% is more commonly specified. it could significantly differ from the settling time at 18 bit level and, therefore, it should be verified prior to the driver selection. the tiny op-amp ad8021 which combines ultra low noise and a high gain bandwidth meets this settling time requirement. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7641. the noise coming from the driver is filtered by the ad7641 analog input circuit one-pole low-pass filter made by r + , r - and c s . the snr degradation due to the amplifier is : () ? ? ? ? ? ? ? ? ? ? + = ? 2 3 3136 56 20 n db loss ne f log snr where : f -3db is the -3db input bandwidth in mhz of the ad7641 (50 mhz) or the cutoff frequency of the input filter if any used n is the noise factor of the amplifiers ( 1 if in buffer configuration) e n is the equivalent input noise voltage of each op-amp in nv/(hz) 1/2 for instance, a driver with an equivalent input noise of 2nv/hz like the ad8021 and configured as a buffer, thus with a noise gain of +1, the snr degrades by only 0.17 db with the filter in figure 7, and 0.8 db without. ? the driver needs to have a thd performance suitable to that of the ad7641. the ad8021 meets these requirements and is usually appropriate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where dual version is needed and gain of 1 is used. the ad8027 is another option where lower supply and dissipation are desired.
preliminary technical data ad7641 rev. pr e | page 15 of 24 single to differential driver for applications using unipolar analog signals, a single ended to differential driver will allow for a differential input into the part. the schematic is shown in figure 10. this configuration, when provided an input signal of 0 to v ref , will produce a differential v ref with midscale at v ref /2. if the application can tolerate more noise, the ad8138 C a differential driver, can be used. 10pf u2 590 ad8021 analog input (unipolar 0 to 2.5v) 10pf u1 590 ad8021 in+ in- ad7641 10k 10k ref 10 f 15 15 100nf 1nf 1nf figure 10. single ended to differential driver circuit (internal reference buffer used) voltage reference the ad7641 allows the choice of either a very low temperature drift internal voltage reference or an external reference. unlike many adc with internal reference, the internal reference of the ad7641 provides excellent performances and can be used in almost all applications. it is temperature compensated to 1.2v tbd mv with a typical drift of tbd ppm/c, a typical long-term stability of tbd ppm and a typical hysterisis of tbd ppm. however, the advantages to use the external reference voltage directly are : ? the power saving of about 8mw typical when the internal reference and its buffer are powered down ( pdref and pdbuf high ) ? the snr and dynamic range improvement of about 1.7 db resulting of the use of a reference voltage very close to the supply (2.5v) instead of a typical 2.048v reference when the internal buffer is used. to use the internal reference along with the internal buffer, pdref and pdbuf should both be low. this will produce a voltage on refbufin of 1.2 v and the buffer will amplify it resulting in a 2.048 v reference on ref pin. it is useful to decouple the refbufin pin with a 100 nf ceramic capacitor. the output impedance of the refbufin pin is 16 k?. thus, the 100 nf capacitor provides an rc filter for noise reduction. to use an external reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows for the 1.2 v reference to be applied to refbufin. to use an external reference directly on ref pin, pdref and pdbuf should both be high. it should be noted that the internal reference and internal buffer are independent of the power down (pd) pin of the part. furthermore, powering up the internal reference and internal buffer requires time due to the charge of the ref decoupling. in both cases, the voltage reference input ref has a dynamic input impedance and requires, therefore, an efficient decoupling between ref and refgnd inputs. when the internal reference buffer is used, this decoupling consists of a 10 f ceramic capacitor ( e.g. : panasonic ecj-3xb0j106 1206 size ). when external reference is used, the decoupling consists of a low esr 47 f tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. temperature sensor the temp pin, which measures the temperature of the ad7641, can be used as shown in figure 11. the output of the temp pin is applied to one of the inputs of the analog switch (e.g. : adg779) and the adc itself is used to measure its own temperature. this configuration could be very useful to improve the calibration accuracy over the temperature range. c c ad8021 in ad7641 in temperature sensor adg779 temp analog input (unipolar) figure 11. use of the temperature sensor
ad7641 preliminary technical data rev. pr e | page 16 of 24 power supply the ad7641 uses three sets of power supply pins: an analog 2.5 v supply avdd, a digital 2.5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.3 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 7. the ad7641 is independent of power supply sequencing and thus free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range as shown in figure 12. figure 12. psrr vs. frequency conversion control figure 13 shows the detailed timing diagrams of the conversion process. the ad7641 is controlled by the signal cnvst which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conversion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert figure 13. basic conversion timing although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. for applications where the snr is critical, the cnvst signal should have a very low jitter. some solutions to achieve that are to use a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock as shown in figure 7. t 9 t 8 reset data bus busy cnvst figure 14. reset timing
preliminary technical data ad7641 rev. pr e | page 17 of 24 interfaces digital interface the ad7641 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7641 digital interface also accommodates both 2.5v, 3.3v or 5v logic with ovdd either at 2.5v or 3.3v. ovdd defines the logic high output voltage. in most applications, the ovdd supply pin of the ad7641 is connected to the host system interface 2.5v or 3.3v digital supply. finally, except in 18 bit interface mode, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7641 in multi-circuits applications and is held low in a single ad7641 design. rd is generally used to enable the conversion result on the data bus. t 1 t 3 t 4 t 11 cnvst busy data bus cs = rd = 0 t 10 previous conversion data new data figure 15. master parallel data timing for reading (continuous read) parallel interface the ad7641 is configured to use the parallel interface with either a 18-bit, 16-bit or 8-bit bus width according to the table 6. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figure 16 and figure 17. when the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. that avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. please refer to table 6 for a detailed description of the different options available. current conversion busy data bus cs rd t 12 t 13 figure 16. slave parallel data timing for read (read after convert) t 1 t 3 t 4 cs = 0 cnvst, rd busy previous conversion t 12 t 13 data bus figure 17. slave parallel data timing for reading (read during convert) cs byteswap pins d[15:8] hi-z high byte low byte hi-z hi-z high byte low byte hi-z t 12 t 12 t 13 pins d[7:0] rd figure 18. 8-bit and 16-bit parallel interface
ad7641 preliminary technical data rev. pr e | page 18 of 24 t 3 busy cs, rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 161718 d17 d16 d2 d1 d0 x ext/int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 19. master serial data timing for reading (read after convert) serial interface the ad7641 is configured to use the serial interface when mode0 and mode1 are held high. the ad7641 outputs 18 bits of data, msb first, on the sdout pin. this data is synchronized with the 18 clock pulses provided on sclk pin. the output data is valid on both the rising and falling edge of the data clock. that allows a fast serial interface speed by using the same clock edge to output the data from the adc and to sample the previous bit by the digital host. master serial interface internal clock the ad7641 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7641 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 19 and figure 20 show the detailed timing diagrams of these two modes. usually, because the ad7641 is used with a fast throughput, the mode master read during conversion is the most recommended serial mode when it can be used. in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 18 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. to accommodate slow digital hosts, the serial clock can be slowed down by using divsclk. slave serial interface external clock the ad7641 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 21 and figure 22 show the detailed timing diagrams of these methods. while the ad7641 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is particularly important during the second half of the conversion phase because the ad7641 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it be a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high.
preliminary technical data ad7641 rev. pr e | page 19 of 24 ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d17 d16 d2 d1 d0 x 12 3 161718 t 18 busy cs, rd cnvst sync sclk sdout figure 20. master serial data timing for reading (read previous conversion during convert) external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 21 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs and rd are low. the data is shifted out, msb first, with 18 clock pulses and is valid on both rising and falling edge of the clock. among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is to be able to read the data at any speed up to 80 mhz which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the ad7641 provides a daisy-chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 23. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the edge of sclk opposite to the one used to shift out the data on sdout.hence, the msb of the upstream converter just follows the lsb of the downstream converter on the next sclk cycle.
ad7641 preliminary technical data rev. pr e | page 20 of 24 sclk sdout d17 d16 d1 d0 d15 x17 x16 x15 x 1 x0 y17 y16 cs busy sdin ext/int = 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 t 34 x17 x16 x 12 20 rd =0 18 17 34 19 figure 21. slave serial data timing for reading (read after convert) sdout cs sclk d1 d0 x d17 d16 d15 123 161718 t 3 t 35 t 36 t 37 t 31 t 32 t 16 cnvst busy ext/int = 1 invsclk = 0 rd =0 figure 22. slave serial data timing for reading (read previous conversion during convert) cnvst cs sclk sdout rdc/sdin busy busy data out ad7641 #1 (downstream) busy out cnvst cs sclk ad7641 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in figure 23. two ad7641 in a daisy-chain configuration external clock data read during conversion figure 22 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are both low, the result of the previous conversion can be read. the data is shifted out, msb first, with 18 clock pulses and is valid on both rising and falling edge of the clock. the 18 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy chain feature in this mode and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of tbd is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated.
preliminary technical data ad7641 rev. pr e | page 21 of 24 microprocessor interfacing the ad7641 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7641 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7641 to prevent digital noise from coupling into the adc. the following section illustrates the use of the ad7641 with an spi equipped dsp, the adsp-219x. spi interface (adsp-219x) figure 22 shows an interface diagram between the ad7641 and an spi-equipped dsp, adsp219x. to accommodate the slower speed of the dsp, the ad7641 acts as a slave device and data must be read after conversion. this mode also allows the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the 18-bit output data are read with 3 spi byte access. the reading process could be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (timod) =00 by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17mbits/s which allow to read an adc result in about 1.1 s. when higher sampling rate is desired, it is recommended to use one of the parallel interface mode with the adsp-219x. spixsel (pfx) adsp-219x* cnvst ad7641* cs misox sckx pfx or tfsx sdout sclk invsclk ext/int dvdd *additional pins omitted for clarity ser/par rd pfx busy figure 24. interfacing the ad7641 to spi interface
ad7641 preliminary technical data rev. pr e | page 22 of 24 application hints layout the ad7641 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7641 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7641, or, at least, as close as possible to the ad7641. if the ad7641 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7641. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7641 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7641 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplies impedance presented to the ad7641 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supplies pins avdd, dvdd and ovdd close to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad7641 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply is available, to connect the dvdd digital supply to the analog supply avdd through an rc filter as shown in figure 7, and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. the ad7641 has four different ground pins; refgnd, agnd, dgnd, and ognd. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. the decoupling capacitor should be close to the adc and connected with short and large traces to minimize parasitic inductances. evaluating the ad7641 performance a recommended layout for the ad7641 is outlined in the documentation of the eval-ad7641-cb, evaluation board for the ad7641. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval- control brd3.
preliminary technical data ad7641 rev. pr e | page 23 of 24 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) figure 25. 48-lead quad flatpack (lqfp) (st-48) dimensions shown in inches and (millimeters) pin 1 indicator top view 0.266 (6.75) bsc sq 0.276 (7.0) bsc sq 1 48 12 13 37 36 24 25 botto m view 0.215 (5.45) 0.209 (5.30) sq 0.203 (5.15) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) bsc 0.031 (0.80) max 0.026 (0.65) nom 12 max 0.039 (1.00) max 0.033 (0.85) nom 0.008 (0.20) ref 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) controlling dimensions are in millimeters paddle connected to agnd ( this connection is not require d to meet electrical performances ) figure 26. 48-lead frame chip scale package (lfcsp) (cp-48) (dimensions shown in millimeters and (inchs)
ad7641 preliminary technical data rev. pr e | page 24 of 24 ordering guide model temperature range package description package option ad7641ast -40c to +85c quad flatpack (lqfp) st-48 ad7641astrl -40c to +85c quad flatpack (lqfp) st-48 AD7641ACP -40c to +85c chip scale (lfcsp) cp-48 AD7641ACPrl -40c to +85c chip scale (lfcsp) cp-48 eval-ad7641cb 1 evaluation board eval-control brd2 2 controller board eval-control brd3 2 controller board 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 or the eval-control brd3 for evaluation/d emonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners.

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